Tradeoffs in Designing Massively Parallel Accelerator Architectures

Tradeoffs in Designing Massively Parallel Accelerator Architectures

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We use VISBench to examine some important high level decisions for an accelerator architecture. We propose a methodology to evaluate performance tradeoffs against chip area. We propose a memory system based on a cache incoherent shared address space along with mechanisms to provide synchronization and communication. We also examine GPU-style SIMD execution and find that a MIMD architecture is necessary to provide strong performance per area for some applications.to run in parallel on the xPU and CPU. We can ... At the same time, the design cost for custom circuits has grown dramatically. ... Nonetheless, custom circuit design retains significant advantages over synthesis for very high speed designs.


Title:Tradeoffs in Designing Massively Parallel Accelerator Architectures
Author: Aqeel A. Mahesri
Publisher:ProQuest - 2009
ISBN-13:

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