Design Techniques for On-chip Global Signaling Over Lossy Transmission Lines

Design Techniques for On-chip Global Signaling Over Lossy Transmission Lines

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This thesis describes techniques for global high-speed signaling over long (aˆ¼10mm) lossy chip-serial transmission lines. With the increase in clock frequencies to multi-GHz rates, it has become impossible to move data across a die in a single clock cycle using conventional parallel bus-based communication. There are also reliability problems due to timing errors, skew, and jitter in fully synchronous systems. Noise, coupling, and inductive effects become significant for both intermediate length and global routing.The phasor diagram in multi-stage oscillators is first presented to explain the variation of the quality factor in multi-stages. Capacitive coupling is explained in detail. 3.1. Phasor diagram 3.1.1 Single stage LC oscillator The voltage and currentanbsp;...


Title:Design Techniques for On-chip Global Signaling Over Lossy Transmission Lines
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Publisher:ProQuest - 2008
ISBN-13:

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